Applied Materials Unveils Chip Wiring Innovations To Keep Pace With Moore’s Law

The semiconductor industry is striving to keep pace with Moore’s Law and enable more powerful, energy-efficient chips for AI computing. Applied Materials has unveiled crucial chip wiring innovations that will help address key challenges in this pursuit:

Enabling 2nm node manufacturing and beyond: Applied Materials’ new materials in chip wiring will enable the production of logic chips at the 2nm node, where circuits are just two billionths of a meter apart. These advancements will:

• Reduce wiring resistance by up to 25%, improving chip performance and power consumption
• Decrease chip capacitance by up to 3% through the use of innovative materials

Strengthening chips for advanced 3D stacking: The company’s enhanced Black Diamond material not only enables scaling to 2nm and below but also offers increased mechanical strength, which is becoming critical as chipmakers push the boundaries of 3D logic and memory stacking.

• The new material reduces the minimum dielectric constant (k-value), allowing for scaling to 2nm and beyond
• It simultaneously provides higher mechanical strength to support the growing demands of 3D chip stacking

Introducing binary metal liner for ultrathin copper wires: Applied Materials’ latest Integrated Materials Solution (IMS) combines six technologies in one high-vacuum system, including an industry-first combination of ruthenium and cobalt (RuCo) as a liner material. This innovation:

• Reduces the thickness of the liner by 33% to 2nm, creating more room for copper in the wiring trenches
• Improves surface properties for void-free copper reflow
• Lowers electrical line resistance by up to 25%, enhancing chip performance and power efficiency

Growing wiring opportunity and market impact: Applied Materials is the industry leader in chip wiring process technologies, and the company’s served available market opportunity has increased significantly with each node advancement.

• From the 7nm to 3nm node, interconnect wiring steps have tripled, increasing Applied’s served available market opportunity by more than $1 billion per 100,000 wafer starts per month (100K WSPM) of greenfield capacity, reaching approximately $6 billion
• The introduction of backside power delivery is expected to further increase Applied’s wiring opportunity by another $1 billion per 100K WSPM, totaling approximately $7 billion

Broader Implications:
Applied Materials’ chip wiring innovations are crucial for enabling the semiconductor industry to keep pace with the demands of AI computing and the goal of creating trillion-transistor chips. These advancements in materials engineering will help chipmakers overcome the physical challenges of classic Moore’s Law scaling and deliver the performance and energy efficiency required for future AI applications.

However, it is essential to note that these innovations are part of a broader effort within the industry, with other companies and researchers also working on various aspects of chip design and manufacturing to push the boundaries of performance and efficiency. The ultimate success of these efforts will depend on the collective progress made across the semiconductor ecosystem and the ability to integrate these advancements into commercially viable products.